Movidius Myriad 2

Movidius Myriad 2 is a microprocessor from Movidius/Intel.

It is used in the Intel T261 and the Intel T265.

It is aimed at providing intelligence to vision processing on a dedicated SoC, and deliver an extra edge in performance to existing CPU and GPU used in VR hardware.

Features[edit]

The Movidius Myriad 2 is able to perform a staggering 2 trillion of 16-bit operations per second, while only consuming 500 mW. That, and its ability to process visual data more intelligently is attributed to its brilliant SoC architecture design.

Key in reducing its power consumption is the hardware accelerators called SIPP filters, which also plays an important part in to run pre-configured vision processing tasks such as fusing data from different cameras.

The SoC hosts an array of 12 SHAVE Vector processors, the heart of the unparalleled vision processing power of Myriad 2. Each of the processors runs at 600Mhz and handles code branches efficiently.

The Myriad 2 also features two RISC processors.

Hardware[edit]

The Movidius Myriad 2 is offered in two different packages, 225 Ball BGA and 270 Ball BGA with the latter supporting up to 4Gb of DDR 3 RAM. It is built with 2Mb On-Chip memory and 256 KB of L2 cache.

The Myriad 2 SoC supports a rich set of interfaces, that includes I2C, SPI, I2S, USB 3.0, GPIO,1 Gbit Ethernet and a debug interface.

Technical Specifications[edit]

Heterogeneous, high throughput, multi-core architecture based on

12 VLIW 128-bit vector SHAVE Processors optimized for machine vision
Configurable hardware accelerators for image and vision processing, with line-buffers enabling zero local memory access ISP mode
2 x 32-bit RISC processors
Supports data and task parallelism
Programmable Interconnect

Support for 16/32-bit floating point and 8/16/32-bit integer operations
Homogeneous, centralized memory architecture; 2MB of on-chip memory
400 GB/sec of sustained internal memory bandwidth
256 KB of L2 Cache
Power management: 20 power islands; low power states
Nominal 600 MHz operation at 0.9 V
Rich set of interfaces:

12 Lanes MIPI, 1.5 Gbps per lane configurable as CSI-2 or DSI
I2C, SPI for control and configuration
I2S for audio input
Banks of configurable GPIO, PWM
USB3 with integrated PHY
2-Slot SDIO
Debug interface
1 Gbit Ethernet

Available package configurations

MA2150/MA2155: 6.5mm x 6.5mm, 0.4mm pitch, 225 Ball BGA, 1Gb LPDDR II
MA2450/MA2455: 8mm x 9.5mm ,0.5mm pitch, 270 Ball BGA, 4Gb LPDDR III

Advanced low-power 28nm HPC process node

Developer[edit]

Extensive supports and resources such as the SDK, libraries, framework and camera API are provided to developers.

https://www.movidius.com/solutions/software-development-kit

Background[edit]

Founded by Sean Mitchell and Dr. David Moloney in 2005, Movidius held to the belief that hat machine vision applications can only be effective at the network edge, running right beside the sensors providing the input. The Myriad 2, a low power high-performance vision processing unit was born from the lack of a suitable single chip solution that satisfies the vision of Movidius.

References